1. Field of the Invention
This invention is related to the field of processors and, more particularly, to the cancelling of speculative instructions in response to a branch misprediction.
2. Description of the Related Art
Branch instructions present numerous challenges to processor designers. The existence of branch instructions in code, and the mechanisms that the processor includes to handle the branch instructions with high performance, are frequently large factors in determining the overall performance that a user may actually experience when using a system including the processor.
One mechanism frequently used to address the challenges presented by branch instructions is speculative operation. Generally, branch instructions may be predicted (e.g. taken or not taken, for conditional branches, and/or branch target address predictions, for indirect branches and returns) and speculative operation may be performed based on the prediction. Instructions may be speculatively fetched and processed up to and/or including execution prior to resolution of the predicted branch instruction. If the prediction is correct, performance of the processor may be increased due to the speculative processing of the next instructions to be executed after the branch (either those at the branch target address or the sequential instructions). However, if the prediction is incorrect, the speculative instructions must be cancelled. Cancelling the speculative instructions, particularly in wide issue processors, may be complex.
A further difficulty introduced in some instruction set architectures (e.g. the MIPS instruction set architecture) involves the branch delay slot. The instruction in the branch delay slot is typically executed irrespective of whether the branch instruction is taken or not taken. However, for some branch instructions, the instruction in the branch delay slot is architecturally defined to be conditional based on whether the corresponding branch is taken or not taken. If the branch is taken, the instruction in the branch delay slot is executed. If the branch is not taken, the instruction in the branch delay slot is not executed. Thus, the branch delay slot instruction is treated differently for different branches, further complicating the cancelling of speculative instructions. Any type of instruction may be in the branch delay slot, and thus locating the instruction and cancelling or not cancelling the instruction based on which branch instruction that instruction follows is complicated.
A processor implements a mechanism for handling instruction cancellation for mispredicted branch instructions. Particularly, a first tag (referred to herein in certain exemplary embodiments as a branch sequence number) is assigned to a branch instruction. Dependent on the type of branch instruction, a second tag is assigned to an instruction in the branch delay slot of the branch instruction. The second tag may equal the first tag if the branch delay slot is unconditional for that branch, and may equal a different tag if the branch delay slot is conditional for the branch. If the branch is mispredicted, the first tag is broadcast to pipeline stages that may have speculative instructions, and the first tag is compared to tags in the pipeline stages. If the tag in a pipeline stage matches the first tag, the instruction is not cancelled. If the tag mismatches, the instruction is cancelled. Thus, an instruction in the unconditional delay slot is not cancelled (since the second tag equals the first tag for the unconditional delay slot) and an instruction in the conditional delay slot is cancelled (since the second tag equals a different tag). The cancellation mechanism thus may not require special handling of the branch delay slot during cancellation . . . the assignment of the tag may ensure the proper cancellation or non-cancellation of the branch delay slot instruction.
Broadly speaking, a processor is contemplated comprising a control circuit and a pipeline. The control circuit is configured to assign a first tag to a branch instruction and a second tag to a second instruction in a branch delay slot of the branch instruction. The second tag is equal to either the first tag or a different tag dependent on a type of the branch instruction. Coupled to receive the second instruction and the second tag, and further coupled to receive the first tag if the branch instruction is mispredicted, the pipeline is configured to selectively cancel the second instruction responsive to values of the first tag and the second tag.
Additionally, a method is contemplated. A first tag is assigned to a branch instruction. A second tag is assigned to a second instruction in a branch delay slot of the branch instruction. The second tag is equal to either the first tag or a different tag dependent on a type of the branch instruction. If the branch instruction is mispredicted, the second instruction is selectively cancelled responsive to values of the first tag and the second tag.